Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally<1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithography masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
Furthermore, as the demand continues for even higher performance of semiconductor devices, the design rule shrink rate is outpacing the progress of both of the exposure wavelength reduction and the advancement of high Numerical Aperture (NA) lenses. This factor has presented a challenge to lithographers to push optical lithography beyond the limit that was thought possible a few years ago. As is known, Resolution Enhancement Techniques (RETs) have become indispensable in low k1, optical lithography. Strong Off-Axis Illumination (OAI), which uses 2-beam imaging with symmetrical 0th and 1st orders in the lens pupil, can greatly enhance resolution and contrast. Dipole illumination is the most extreme case of OAI, and is capable of providing better imaging contrast with improved process latitude for very low k1 imaging.
However, one of the limitations associated with dipole illumination is that a single illumination only enhances resolution for features that are orthogonal to the illumination pole axis. As a result, in order to take full advantage of dipole illumination during wafer printing, the mask pattern must be converted into horizontal and vertical orientations. Once the mask pattern is converted in this manner, a Y-pole exposure is utilized to image the horizontally oriented features, and a X-pole exposure is utilized to image the vertically oriented features. One important aspect of dipole illumination is that when imaging the horizontally oriented features, the vertically oriented features must be protected (i.e., shielded) so the vertically oriented features are not degraded. The opposite is true when vertically oriented features are imaged (i.e., the horizontally oriented features must be protected).
FIG. 1 illustrates the basic concepts of double dipole imaging. As stated, typically there are at least two exposures when utilizing dipole illumination. In the first exposure, the X dipole aperture 10 provides a maximum aerial image intensity (i.e., maximum modulation) for the vertical portion of the lines 12 to be printed. The resulting image profile is illustrated by line 24 in FIG. 1. In the second exposure, which utilizes the Y-dipole aperture 16, there is no image modulation for lines 12. It is noted, however, that during the second exposure using the Y-dipole aperture, the vertical portions of the lines 12 need to be shielded so that the vertical features formed during the first exposure are not degraded during the second exposure. FIG. 1 illustrates shielding the lines 12 with shields 15, each of which is formed by enlarging the target line 12 in the horizontal direction 20 nm per side. It is noted that the amount of shielding corresponds to the amount that the vertical edges of the feature are extended. For example, assuming an initial line width of 70 nm, each vertical edge would be extended an additional 20 nm, which would result in a total width of shield 15 of 110 nm. As a result of the shielding, when exposing the horizontal lines using the Y dipole aperture, there is substantially no imaging (i.e., modulation) of the vertical features 12. The aerial image is a DC component as shown by line 17 in FIG. 1, which corresponds to the 20 nm shielding. The final aerial image intensity, which is represented by line 14 in FIG. 1, corresponds to the sum of the first exposure using the X dipole aperture and the second exposure using the Y dipole aperture.
It is further noted that, assuming the exposure energy is constant, increasing the width of the shielding of each edge from a 20 nm shield 15 to a 40 nm shield 20 for the vertical lines 12 causes the minimal intensity level of the resulting image to shift to a lower level. This is represented by line 22 in FIG. 1, which represents the aerial image associated with the vertical portions of the features. As shown, the aerial image 22 is just a DC component. However, it is lower than the DC component 17 associated with the 20 nm shield. As a result, the composite image 19 formed utilizing the 40 nm shielding provides better imaging results than the composite image 14 formed utilizing the 20 nm shielding.
When utilizing dipole illumination techniques, as a result of the need to separate the horizontally and vertically oriented features, one of the challenges for the lithographer is determining how to convert the original IC design data into its horizontal or vertical pattern components and generate two masks for the dual exposure process that can take full advantage of the dipole imaging performance.
FIG. 2 is a flowchart which depicts an exemplary rule-based decomposition process for generating the horizontal and vertical masks based on a target design. Referring to FIG. 2, the first step (Step 200) is to decompose or separate the original layout 19 (i.e., target design) into primarily horizontal features and vertical features. The next step (Step 220) is to apply shielding to both masks, using rule-based edge treatment. Typically, the shielding rules are empirical determined (e.g., the rules are defined using experimental results at a given number of pitch intervals). The third step (Step 240) is to apply scattering bars (i.e., OPC technique) to both dipole masks (horizontal and vertical). Specifically, after the shielding has been applied in the first step, scattering bar OPC is then applied to each of the orientations. The scattering bars (SB) are applied only along the orientations perpendicular to the pole (i.e., vertical SBs on the vertical mask and horizontal SBs on the horizontal mask). The fourth step (Step 260) is to provide negative serif treatment (also known as widen/deepen) to concave corners. The purpose is to provide cuts-outs in the shielding, near concave comers, which allow enough light to define the edges along the high modulation orientation, causing better line-definition in the concave comers. The final step (Step 280) in this approach is to apply fine biasing along the critical high modulation orientations for each mask. The horizontal mask will have fine biasing treatment along the horizontal edges and the vertical mask will have the fine biasing along the vertical edges.
Currently known techniques for generating the horizontal and vertical masks do not always produce optimal results when attempting to generate such masks for complex structures. For example, utilizing known techniques such as the one disclosed in the flowchart of FIG. 2, it is sometimes difficult, for example, to provide proper shielding for complex structures, such as, “jogs” (i.e., short changes in either the vertical or horizontal direction, for example, a short vertical step, between two long horizontal lines), short “S” turns and/or U-shaped patterns in the design. Moreover, it is sometimes difficult to determine whether or not a given structure of the target design should be treated as a horizontal structure or a vertical structure when initially generating the horizontal and vertical masks. As a result, it was often necessary to have an experienced mask designer involved with the generation of the horizontal and vertical masks for addressing and rectifying the foregoing issues in order to generate acceptable mask designs.
Accordingly, there exists a need for a method which allows for the generation of both horizontal and vertical masks utilized in conjunction with double dipole imaging, which eliminates the issues and disadvantages associated with prior art techniques for generating horizontal and vertical masks.